1. Field of the Invention
The present invention relates to a thin film transistor device in which thin film transistors using film of amorphous silicon, polysilicon or other semiconductor for an active layer are integrated and a method of manufacturing the device.
2. Description of the Prior Art
In recent years, a display for personal computers and a television, which use a liquid crystal display panel, have been generally used. The liquid crystal display panel is also used for a display of cell phones, PDAs (Personal Digital Assistant), and the like. Further, development of an organic EL display panel, which can save more power than the liquid crystal display panel, is in progress as well in recent years, and the organic EL display panel has already been commercialized in some products.
In the liquid crystal display panel and the organic EL display panel, a large numbers of picture elements (sub pixels) are generally arrayed in a matrix state, and each picture element is provided with a thin film transistor (hereinafter, also referred to as TFT) as a switching element. A display panel having such a structure is referred to as an active matrix display panel.
A general TFT is provided with a semiconductor film formed on an insulated substrate, a gate insulating film formed on the semiconductor film, and a gate electrode formed on the gate insulating film. However, positions of the gate electrode and the semiconductor film are opposite in the case of an inversely staggered TFT.
When an amorphous silicon film is used as the semiconductor film, it is necessary that an IC (Integrated Circuit) for panel driving be connected outside the display panel and the IC for panel driving drive the display panel because carrier mobility of amorphous silicon is small. On the other hand, when a polysilicon film is used as the semiconductor film, a drive circuit constituted by TFTs can be integrally formed on the display panel because carrier mobility of the polysilicon film is large. This reduces the number of parts and the number of manufacturing processes of an apparatus using the display panel, and a product cost can be reduced.
FIGS. 1A to 1C are views showing the structure of a conventional TFT, where FIGS. 1A, 1B and 1C are a plan view of the TFT, a sectional view at I-I line in FIG. 1A, and a sectional view at II-II line in FIG. 1A, respectively.
A silicon oxide film as an underlying insulating film 11 is formed on a glass substrate (insulated substrate) 10. The polysilicon film as a semiconductor film 12 is formed on a TFT formation region of the underlying insulating film 11.
The silicon oxide film as a gate insulating film 13 is formed on the underlying insulating film 11 and the semiconductor film 12, and a gate electrode 14 made of metal is formed on the gate insulating film 13. The gate electrode 14 is formed so as to cross above the semiconductor film 12.
A pair of highly concentrated impurity regions (source/drain regions) 12a, 12b, which have been formed by implanting p-type or n-type impurities using the gate electrode 14 as a mask, are provided for the semiconductor film 12.
Incidentally, in the case of the TFT, where the semiconductor film 12 is made up of polysilicon and the gate insulating film 13 is made up of silicon oxide as shown in this example, it is known that a threshold voltage is negative (a few −V) if dopant (impurities) is not added at all to a channel region of the semiconductor film 12.
Since CMOS (Complimentary Metal Oxide Semiconductor) where the p-type TFT and the n-type TFT are arranged in a pair is used in the drive circuit of the display panel, a leakage current occurs to increase power consumption unless the threshold value voltage is adjusted such that both of the p-type TFT and the n-type TFT are turned off when a gate voltage is 0V. For this reason, the p-type impurities such as boron (B) is introduced into the entire semiconductor film 12 before forming the gate electrode 14 to control the threshold voltage such that both the p-type TFT and the n-type TFT are turned off when the gate voltage is 0V.
There exist an ion implantation method, an ion doping method, and a vapor-phase doping method, for example, as a method to introduce the p-type impurities into the semiconductor film 12. Note that, in the present invention, a method in which mass separation is performed and only a target ion is implanted into the semiconductor film is referred to as the ion implantation method, and a method in which the impurities are accelerated without performing mass separation and implanted into the semiconductor film is referred to as the ion doping method. As the ion doping method, there exists a method in which material gas such as diborane (B2H6), for example, is excited by RF (Radio Frequency) power to generate boron ion and the boron ion is accelerated into energy having a few keV to 100 keV to be implanted into the semiconductor film. Further, as the ion doping method, there exists a method in which ion is generated by ark discharge using filament instead of the above-described RF electric power and the ion is accelerated to be implanted into the semiconductor film, or a method in which ion beam generated by the ark discharge is implanted into the semiconductor film while scanning the beam.
The following method is used in the case of forming the polysilicon film containing boron (B) as the p-type impurities by the vapor-phase doping method.
First, after having formed the underlying insulating film 11 on the substrate 10, the amorphous silicon film is formed on the underlying insulating film 11 by a plasma CVD (Chemical Vapor Deposition) method. At this point, diborane (B2H6) gas is mixed into silane (SiH4) gas, which is a material, to form the amorphous silicon film containing boron (B).
Subsequently, laser is irradiated onto the amorphous silicon film to transform the silicon into polycrystalline. Thus, the polysilicon film containing boron is obtained. Then, patterning is performed to the polysilicon film into a predetermined shape.
In the vapor-phase doping method, boron quantity per unit volume (volume density) in a film thickness direction of the semiconductor film becomes uniform.
The following method is used in the case of forming the polysilicon film into which the p-type impurities have been introduced by the ion implantation method or the ion doping method.
First, after having formed the underlying insulating film 11 on the substrate 10, the amorphous silicon film is formed on the underlying insulating film 11 by the plasma CVD method. Subsequently, laser is irradiated onto the amorphous silicon film to transform the silicon into polycrystalline, and the polysilicon film is obtained.
Next, patterning is performed to the polysilicon film into a predetermined shape by the photolithography method. Then, ion implantation or ion doping of boron (B) as the p-type impurities, for example, are performed to the polysilicon film.
However, the inventors think that the above-described conventional manufacturing method of TFT has the following problems.
Generally, in the TFT used in the liquid crystal display panel or the like, the edge portion of the semiconductor film is processed so as to have gradient as shown in FIG. 1C for the purpose of securing withstand voltage for the gate insulating film 13. (refer to Patent Application Publication (KOKAI) 2000-31493, for example). Hereinafter, the gradient portion of the silicon film is referred to as a gradient section.
As described above, since the boron quantity per unit volume (volume density) in the film thickness direction of the semiconductor film is uniform in the vapor-phase doping method, the boron quantity (surface density) per unit area of the gradient section in the channel region is smaller than that of a central section (hereinafter, also referred to as a flat section) of the channel region when the TFT is viewed from above. Accordingly, the threshold voltage at the gradient section becomes lower than the threshold value voltage at the flat section by approximately −1V to −2V.
FIG. 2 is the view schematically showing the current-voltage characteristic (I-V characteristic) of the conventional TFT (n-type TFT and p-type TFT). As shown in FIG. 2, the gradient section of the n-type TFT has a small channel width and becomes a parasitic transistor with a low threshold value voltage, and the current actually flowing in the TFT is one where the characteristic of the gradient section is added to the characteristic of the flat section, which is the characteristic having a so-called hump. Note that, in the p-type TFT, the characteristic of the gradient section is masked by the characteristic of the flat section, and a change of the threshold voltage due to the influence of the gradient section does not occur.
In the case where the n-type TFT and the p-type TFT having such characteristics constitute the CMOS, it is difficult to control a doping quantity of the p-type impurities into the semiconductor film such that both TFTs are turned off when the gate voltage is 0V because the threshold of the n-type TFT and the threshold of the p-type TFT are close.
Although distribution of the p-type impurities are not uniform in the thickness direction of the semiconductor film when the polysilicon film, into which the p-type impurities was introduced by the ion implantation method or the ion doping method, has been formed, the surface density of the p-type impurities of the gradient section becomes smaller than that of the flat section, which is the same as the case of the vapor-phase doping method. Furthermore, a problem similar to the one described above occurs in the inverted staggered TFT as well when the edge portion of the semiconductor film is gradient.
Note that Patent Application Publication (KOKAI) 2000-77665 proposes that ion implantation of Ar be performed to the edge portion of the polysilicon film to give damage thereto into an amorphous state, and a drive capability of the parasitic transistor be reduced. However, it is considered that annealing in a post-process causes recrystallization depending on the concentration of Ar and the influence of the edge portion may appear.